1. Field of the Invention
This invention concerns a voltage level converting circuit, and more particularly a voltage level converting circuit for converting a read level voltage to a write level voltage, and being installed in a nonvolatile memory, such as EPROM and EEPROM, etc.
2. Description of the Prior Art
Both the EPROM (Erasable Programmable Read Only Memory) and the EEPROM (Electrical Erasable Programmable Read Only Memory) retain data even if their power source supply is cut off. The data in the EPROM may be erased by ultra violet rays, and the data in the EEPROM may be erased electricallY, and both can be rewritten with new data.
FIG. 1 is a block diagram of a conventional EPROM. In FIG. 1, numeral 11 designates a control circuit for selectively outputting a read level voltage VCC, e.g., +5 volt, or a write level voltage VPP, e.g., +12.5 volt. Numeral 13 designates a voltage level converting circuit for converting a write enable signal WE of the read level voltage VCC, which is supplied to an input terminal 10, to a write level voltage VPP. A depletion type MOS transistor 12 is biased with the write level vOltage VPP, and supplied with an output signal of the voltage level converting circuit 13. Another depletion tYpe MOS transistor 14 is biased with the read level voltage VCC, and supplied with the WE signal through two inverters 15 and 16, at the gate electrode thereof. The output of the transistors 12 and 14 are supplied to a column decoder 17 and a row decoder 18.
Numeral 19 shows a data-write control circuit, which includes a voltage level converting circuit 20 for converting a write-data D of the read level voltage, which is supplied to a terminal 9, to the write level voltage. The control circuit 19 further includes an enhancement MOS transistor 21 being supplied the output of the voltage level converting circuit 20. The MOS transistor 21 acts as a load during a write operation, and supplies the write level voltage VPP to a column gating circuit 22, in response to the output signal of the voltage level converting circuit 20. The column gating circuit 22 is provided with a sense amplifier 23.
The output of the column decoder 17 is selectively supplied to corresponding gate transistOr 25, to select bit line 24. On the other hand, an output of row decoder 18 is selectively connected to control gate electrodes of nonvolatile MOS transistors in a memory cell arraY 27.
In this construction, a write operation is performed by selecting a memory transistor, e.g., a transistor 28, by setting one of the output signals of the column decoder 17 and the row decoder 18 corresponding to the transistor 28 to the write level voltage VPP. Namely, at first, the write enable signal WE is set to "O" level to obtain an output signal of a write level voltage corresponding to a "1" level from the voltage level converting circuit 13. In this condition, the transistor 12 supplied with the signal of "1" level, changes to the conductive state to supply the write level voltage VPP to the column decoder 17 and the row decoder 18. The column decoder 17 and the row decoder 18 output an output signal of the write voltage level in response to an address signal (not shown), respectively. In accordance with the output signal of the column decoder 17, for example, a gate transistor 25 is rendered conductive, and a bit line 24 is selected.
In this way, a transistor 28, which is positioned at the cross point of the selected bit line 24 and word line 26 is selected. In this state, in the case where the write-data D is "0" level, data is written into the transistor 28, since the transistor 21 is conductive because it is supplied with the level converted output signal of the VPP level from the voltage level converting circuit 20.
FIG. 2 is a circuit diagram of a conventional voltage level converting circuit used as the voltage level converting circuits 13 and 20, in FIG. 1. An input signal Sin having the read level voltage VCC corresponding to the logical "1" level thereof is supplied to a terminal 36, and is transferred to the gate electrodes of a P-type MOS transistOr 33 and an N-type MOS transistor 34 through inverters 29, 30, and transfer gate transistors 31 and 32. The inverters 29 and 30 are biased with the VCC voltage and the ground level voltage VSS. Thus, the signal at the node A swings between the voltage level VCC and ground level VSS, namely 0 volt.
The transfer gate transistor 31 acts to transfer the VCC level signal to the node B, and to prevent the transfer of the VPP level at the node B to the node A. The transfer gate transistor 32 becomes nonconductive when the gate voltage VPP is "0" level, and prevents a formation of a conductive path between the node A and the node B when the VPP is 0 volt. The drain electrode of the transistors 33 and 34 are connected in common, and connected to an output terminal 37 to output an output signal OUT.
The output signal OUT is supplied to the gate electrode of a P-type MOS transistor 35, which is connected between the write level voltage VPP and the node B. The gate electrode of the transfer gate transistor 31 is supplied with the read level voltage VCC, and the gate electrode of the transistor 32 is supplied with the write level voltage VPP. The source electrode of the transistor 33 is suppled with the write level voltage VPP, and the source electrode of the transistor 34 is connected to around level VSS.
In this circuit, when the input signal Sin changes to "1" level, namely the VCC level, the signal at the node A changes to "1" level, namely the VCC level. Thus, the transistor 33 changes to a non-conductive state, and the transistor 34 changes to a conductive state, to provide the output signal OUT at a "0" level. In this state, the P-type MOS transistor 35 is supplied with the "0" level output signal OUT at the gate electrode thereof. Thus, the transistor 35 changes to a conductive state to supply the write level voltage VPP to the node B, to speed up the change of the transistor 34 to the conductive state.
On the other hand, when the input signal Sin changes to "0" level, the transistor 33 changes to a conductive state, and the transistor 34 changes to a non-conductive state to get an output signal OUT of "1" level. In this state, the transistor 35 changes to a non-conductive state as being supplied with the high level signal at the gate electrode thereof.
However, in this construction, the voltage level present at node B occasionally becomes insufficient to make the transistor 34 conductive due to the voltage drop at the transfer gate transistors 31 and 32, even if the input signal Sin is at level "1".
FIG. 3 is a circuit diagram of another conventional voltage level converting circuit designed to improve the above described defect of the circuit of FIG. 2.
In this circuit, the gate electrode of the transistor 34 is directly connected to node A to eliminate the voltage drop due to the transfer gate transistors 31 and 32.
However, in this construction, there is another problem. Namely, in the case where an ESD (Electro Static Discharge) is supplied to a terminal for the write level voltage VPP during a time when no power is supplied to VPP and VCC, and the node A is in an imaginarY grounding state, the surge voltage is supplied to the output terminal 37, since the transistor 34 is non-conductive and the transistor 33 is conductive. As a result, the control gate and the drain of the memory cell transistor in FIG. 1 becomes high level. Therefore, a stress is applied to the memory cell transistor to inject the charge into a floating gate, or to perform an unintentional writing. Thus, data in the memory may be disturbed.